CCIX Consortium Releases Evaluation Version of Specification
BEAVERTON, Ore., August 5, 2019 -- The CCIX Consortium (CCIX) announced the public availability of the CCIX Base Specification Revision 1.0a v1.0 for evaluation to enable a broader understanding and adoption of CCIX technology. The public version of the CCIX specification provides an opportunity for non-consortium members to review the CCIX Base Specification, which has been available to CCIX Consortium members since June 2018. The CCIX Consortium is also releasing a full version of the CCIX Base Specification Revision 1.0a to members.
The CCIX specification is an interconnect standard which provides cache coherency for accelerators and memory expansion peripheral devices connecting to processors independent of the instruction set architectures (ISAs) in today’s heterogeneous compute architectures. CCIX extends the benefits of peer processing to acceleration devices, allowing system designers to take advantage of task optimized processing to deliver more power, performance and cost optimized solutions. The CCIX specification utilizes PCI Express technology, allowing system architects to easily implement CCIX in alignment with current and future PCIe specifications and benefit from its evolving data rates.
The CCIX Consortium is providing a public version of the CCIX Base Specification 1.0a, allowing non-member companies to explore the key benefits of CCIX’s chip-to-chip interconnect. The public version of the CCIX Base Specification 1.0a includes all of the Base Specification 1.0a
chapters with the exception of the CCIX PHY chapter, which remains limited to CCIX Consortium members.
The full version of the CCIX Base Specification 1.0a, reserved for Consortium members, includes specific clarifications in the Transaction layer, Datalink layer, and Reliability and Serviceability (RAS), to better help Consortium Members’ implementation of the CCIX Standard.
Membership in the CCIX Consortium also provides access to the rights and protections under the intellectual property rights (IPR) policy to use CCIX technology and early access during the development of future specifications. Non-members will need to join the CCIX Consortium to use CCIX technology in their products.
“As the industry demand for a robust cache-coherent interconnect for processors and devices grows, it is important that system designers understand how CCIX can help them optimize and simplify their heterogeneous systems,” said Gaurav Singh, CCIX Chairman. “By providing this public version of the CCIX specification, non-consortium members can identify how our open interconnect enables cache coherency, additional bandwidth and reduced latency across all PCI Express generations and benefits not only their own designs, but the industry as a whole.”
Source: CCIX Consortium
