New Chip Approaches Seek to Keep Up with AI
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Exploding data sets and complex software have made it harder for single-purpose platforms like ASICs to keep up with the growing demands of enterprise datacenters. Heavy investments in chip design and development therefore run the risk of obsolescence by the time they are deployed.
In response, an ecosystem is emerging around greater programmability that promises to optimize hardware while retaining the performance benefits of custom silicon. Among the approaches are software-defined computing platforms promoted as “future-proof” at a time when cloud and datacenter hardware are tackling complex, data-driven AI, machine learning and HPC workloads.
Startups are promoting this future-proofing, or composable, approach as a way to keep up with web-scale applications while adding new tools like embedded analytics to provide visibility into chip operations, including debugging tools.
For example, SimpleMachines Inc., a four-year-old platform startup, recently announced a partnership with U.K.-based embedded analytics vendor UltraSoC. The combination would give users a window into how hardware and software are behaving in applications ranging from visual cognition and language comprehension to security.
SimpleMachines touts is composable computing platform as addressing the inability of enterprise hardware in general and ASICs and other custom chips specifically to keep pace with rapid technological change wrought by AI and machine learning. Addressing the time and money needed to design and deploy chips, the company’s composable approach breaks down workloads into four behavior patterns. Each is compiled on silicon “on the fly” to create what is promoted as an evolving platform that can adjust to the workload requirements posed by machine learning, robotics and data analytics.
The partnership with UltraSoC (pronounced Ultra-Sock) provides the embedded analytic capabilities used to track and understand hardware and software behavior under stress.
The U.K. company’s semiconductor IP is “embedded into chips to give insight and analytics into their behavior in operation and deployment,” said UltraSoC CEO Rupert Baines. The chip analytics act as a “burglar alarm” when anomalies are spotted indicating a hack, ranging from unauthorized access to a specific area of memory to suspicious network activity.
UltraSoC’s embedded analytics IP and debugging tools are also used to monitor and boost the performance of AI chips, servers and HPC platforms. Early customer PMC-Sierra, the fabless semiconductor company, used analytics and other monitoring tools within its disk drive controllers. The monitors were used to collect detailed data on chip behavior while also shedding light on the performance of server infrastructure those systems-on-chip support.
“The hardware-based approach can detect hard-to-identify issues [making] it substantially easier to home in on non-fatal bugs,” the company said.
The partnership with SimpleMachines aims squarely at traditional “hard-wired” frameworks for handling data-intensive applications, primarily custom ASICs. The future-proofing feature is aimed at cost in terms of time and money required for ASIC development as data volumes continue to soar.
“Clever new hardware architectures…often overlook how the software developer will use, debug, or understand that architecture,” noted Gajinder Panesar, UltraSoC’s CTO.
The embedded analytics specialist is also part of a chip design automation team recently announced by the Defense Advanced Research Projects Agency. UltraSoC and Arm are providing semiconductor IP to team leader and design automation specialist Synopsys (NASDAQ: SNPS) for a generic SoC that implements a “security engine.”
Ultimately, the DARPA project seeks to embed security into chip designs and, with it, the semiconductor supply chain, while allowing silicon architects to implement system-level synthesis tools.
