PCI Express VIP from Avery Design Systems Selected by Fungible 

TEWKSBURY, Mass., Feb. 28, 2022 — Avery Design Systems, a leader in functional verification solutions, today announced its PCI Express Verification IP (VIP) has been selected by Fungible Inc., a data center infrastructure company, to ensure compliance and connectivity of its Fungible Data Processing Unit (DPU). The Fungible DPU is an industry-first and addresses the most challenging requirements in hyperscale data centers running data-intensive applications and delivers radically improved performance and cost efficiencies.

Fungible Data Processing Unit

“As the industry embraces data-centric computing we are trailblazing a whole new category of microprocessor. Our silicon is front and center to how we maintain that leadership. Avery Design Systems is a leader in PCIe VIP and has been a big part of our success enabling us to consistently ensure every generation of our silicon is bug free, industry compliant and operating at the highest levels of efficiency,” said Chakravarthy Kosaraju, senior vice president, silicon design and validation at Fungible.  

The Avery PCI Express VIP is a comprehensive verification solution featuring an advanced UVM environment that supports the latest features and capabilities in the high-speed interconnect protocol.

“Avery strives to deliver best-in-class, robust, pre-validated PCIe IP solutions which streamline the design and verification process for our customers,” said Christopher Browy, vice president of sales and marketing at Avery Design Systems. “We are proud to see how Fungible has leveraged the advanced capabilities of our VIP to ensure the Fungible DPU remains on the leading edge, offering the industry’s only purpose-built processor for executing data centric computations.”

Avery is a leader in PCIe VIP and works with its ecosystem partners to ensure a comprehensive and leading-edge IP solution. The Avery SystemVerilog/UVM VIP solution includes models, protocol checking, compliance test suites, and Virtual Host QEMU co-simulation – enabling our customers to tackle new PCIe 6.0 design and verification challenges even when no mainstream commercial platforms support the latest standards.

Avery Design Systems

Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for gate-level X-pessimism verification and real X root cause and sequential back tracing; and robust core-through-chip-level Verification IP for PCI Express, CXL, CCIX, Gen-Z, USB, AMBA, UFS, MIPI CSI/DSI, I3C, DDR/LPDDR, HBM, ONFI/Toggle/NOR, NVM Express, SATA, AHCI, SAS, eMMC, SD/SDIO, CAN FD, and FlexRay standards. The company has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information is available at www.avery-design.com.

Source: Avery Design Systems